The invention relates to thin film transistors and in particular to a method of manufacture of a device including a number of thin film transistors.
Thin film transistors (TFTs) are widely used in a number of applications. A particularly important application for thin film transistor technology is in the field of active matrix liquid crystal displays. However, this is not the only application; another example is in the field of X-ray detectors which may include a photodiode array in which each photodiode is connected to a corresponding thin film switching transistor.
A typical TFT on an active plate of an active matrix liquid crystal display is illustrated in FIG. 6. A gate 51 extends laterally from a row electrode 53, a semiconductor region 55 is provided on the gate extension and source 57 and drain 59 metallisations are provided over the semiconductor region, one of the source and drain being connected to a column electrode 61 and the other to a pixel electrode 65, generally made of transparent indium tin oxide (ITO). The source, gate and drain and the semiconductor region define a thin film transistor 63.
The current state of the art process for making arrays of thin film transistors, for example for making active matrix liquid crystal displays (AMLCDs), involves depositing material in sheet form and then using photolithography and etching to pattern the material. Typically, five mask steps are used in a TFT design, although some processes have been proposed with four mask steps. The need to deposit material layers, define photoresist on each layer and then etch or develop away typically 95% of each material layer limits the possible cost savings. Moreover, the high performance patterning tools used have high capital cost, limited throughput and use large quantities of costly photoresist and developer.
As an alternative, it has been proposed to directly print resist in the desired pattern, instead of coating, exposing, developing and baking photoresist in the conventional photolithography process. This would save costs by increasing throughput, reducing capital costs and lowering materials costs as compared to a conventional photolithography process. A more radical option proposed is to directly print the material required, or a precursor of that material, thus also eliminating the blanket deposition, resist stripping and etching processes.
Unfortunately, printing processes have poor resolution and alignment accuracy compared with conventional photolithography. Typical printing resolutions are of order 10 xcexcm and alignment accuracy is of order 10 xcexcm for offset printing techniques. These compare unfavourably to the resolution of 4 xcexcm and alignment accuracy of 1.5 xcexcm achieved using conventional photolithography for AMLCDs. If conventional thin film transistor (TFT) designs on the active plates of conventional AMLCDs are scaled up to printing design rules, then the resulting TFTs would have too high a parasitic capacitance to provide an adequate performance.
A second problem is that printing processes such as gravure-offset printing, and other forms of printing, tend to leave hairs or tails of material from the trailing edge of features. These can lead to short circuits in the TFTs and other faults in AMLCDs. With conventional AMLCD TFT and pixel designs, the TFT is placed in the corner of each pixel, with the gate defined by a protrusion from a row line. If a printing technology such as gravure-offset is used, the hairs could lead to undesirable features such as variable capacitive coupling from the gate to the pixel, leading to display effects such as flicker.
A partial solution to the problems of printing TFTs is proposed by M. Ie Contellec et al, J. Non-Cryst. Solids, Vol 97and98 (1987) pages 297 to 300, xe2x80x9cVery Simple a-Si TFT Fabrication Process for LCD-TV Applicationxe2x80x9d. They propose a TFT design and an associated process in which the design is tolerant to misalignment between the two mask layers. However, the process proposed has a number of disadvantages. The column electrodes are made of Indium Tin Oxide (ITO) which has a high resistivity which limits the display size. The two-mask top gated structure proposed results in a high parasitic capacitance loading on the row electrode, which also limits display size. The semiconductor layer is exposed to the light in a transmissive AMLCD, which would lead to unacceptable leakage current unless an additional light shield layer is used.
Instead of the two-mask top-gated structure, it would be preferred to use a bottom gated structure, which has become the industry standard. The basic layout of the design of le Contellec et al could be translated into a bottom gated process with a higher mask count. However, given the coarser resolutions of printing technologies, the resulting TFTs would have too high a parasitic capacitance to provide a good performance in an AMLCD.
A number of other suggestions for fabricating devices using printing for patterning have also been published.
For example, Eiji Kaneko describes in Displays, Volume 14, Number 2, (1993) xe2x80x9cA new fabrication technology for very-large-area TFT-LCDsxe2x80x9d, an all-printed process for manufacturing active matrix displays. Likewise, Y. Mikami et al also describe, in IEEE Transactions On Electron Devices, vol. 41, no. 3, March 1994, xe2x80x9cA New Patterning Process Concept for Large-Area Transistor Circuit Fabrication Without Using an Optical Mask Alignerxe2x80x9d, an all-printed TFT LCD.
However, these publications do not disclose a solution to the problems of excessive parasitic capacitance or of the possible short circuits from xe2x80x9ctailsxe2x80x9d of material extending from printed regions.
Accordingly, there remains a need for an improved method of fabricating thin film transistors, and devices including thin film transistors such as AMLCDs.
According to a first aspect of the invention there is provided a method of manufacturing a plate having an array of thin film transistors including the steps of: forming and patterning by a lower definition process a layer defining row conductors extending across a substrate, forming and patterning by a lower definition process semiconductor regions to form the channel regions of thin film transistors, the semiconductor regions being vertically aligned with regions of the row conductors which regions form the gates of the thin film transistors; forming a gate insulation layer between the layer defining row conductors and the semiconductor regions; and depositing and patterning the sources and drains of the thin film transistors using a higher definition process.
The method forms the plate in such a way that only one layer, the layer defining the source and drain, needs to be accurately defined by a high definition (resolution) process. This layer defines the channel length. Other layers can be patterned by a lower definition process, e.g. printing. In this way, the method can manufacture plates more economically.
In embodiments of the invention a number of different processes may be used for the lower definition process and for the higher definition process, depending on the resolution required. As will be appreciated by the skilled person, photolithography is a particularly useful high definition process. Projection photolithography may be used, for high definition. As an alternative, photolithography may be carried out using a proximity aligner; this is sufficient to define a channel length of around 7 xcexcm with sufficient accuracy.
The process with a lower definition may be a low resolution photolithography process, such as with a proximity aligner, or alternatively a printing process such as gravure-offset printing.
Where printing is used to pattern a layer the printing process may directly print the layer. This avoids material wastage.
The row conductor may have a substantially uniform width across the region of the substrate in which thin film transistors are formed. The semiconductor region may be substantially in the form of rectangles extending with the long axes substantially parallel to the rows. With this relatively simple form the semiconductor region may be printed without trailing hairs having a negative effect.
The method may be applied to the manufacture of an active plate for a active matrix liquid crystal display (AMLCD). The method may accordingly additionally include forming and patterning pixel electrodes using a lower resolution process.
The source electrode may be formed on one side of the drain electrode and a finger electrode may extend around the drain electrode to the other side of the drain electrode. This effectively provides a pair of source electrodes arranged on either side of the drain electrode, which improves alignment tolerance. A subsidiary benefit is that the arrangement can deliver the desired effective aspect ratio.
The printing may be carried out using any suitable printing process, such as gravure-offset printing, although alternative printing techniques may also be used.
The row conductors may be printed in a row direction and the semiconductor regions may be printed in the same row direction.
The pixel electrodes may be printed in a direction substantially perpendicular to the row direction. The structure may have gaps between pixel electrodes and the row conductors longer than the length of trailing tails or hairs from the printing process, which may be of order 10 xcexcm long.
In these ways, the effects of any tails or hairs trailing from the printed regions may be minimized.
The method may be used to fabricate bottom gated TFTs in which the row electrode acting as gate is formed under the semiconductor acting as the channel of the TFTs. The higher definition process may then be used to form metallisations for source and drain over the semiconductor layer.
The semiconductor region may be a stack consisting of a lower layer of lower doped semiconductor and an upper layer of higher doped semiconductor, and the method may include the step of etching back the upper layer using the source and drain metallisation as a mask.
The invention is not limited to the specific layers and patterning steps listed above. Accordingly, a second aspect of the invention provides a method of manufacturing a plate having an array of thin film transistors, including depositing and patterning a plurality of layers to define the thin film transistors, wherein one of the plurality of layers is patterned using a higher definition process and others of the plurality of layers are patterned using a lower definition process.
In general, it is more expensive to pattern layers with a higher resolution than a lower resolution. Accordingly, by patterning only one layer of the thin film transistor with a higher resolution the expense of making a device may be minimized. The higher definition layer may be patterned using photolithography, and the lower definition layer by printing.
One of the layers patterned with a lower definition process may be a row electrode layer defining a plurality of row electrodes extending across the array of thin film transistors with substantially constant width, wherein the thin film transistors are formed vertically aligned with the row electrodes, and wherein the layer defining the source and drain of the thin film transistors is patterned with the higher definition process.
The invention is particularly suitable for manufacturing an active plate of a liquid crystal display, including the steps of forming and patterning by a lower definition process a layer defining row conductors extending across a substrate, forming a gate insulation layer over regions of the row conductors; and forming and patterning by a lower definition process semiconductor regions over the gate insulation layer to form the channel regions of thin film transistors so that the regions of the row conductors under the semiconductor regions act as gates; depositing and patterning a metallisation layer with a higher definition process to define the sources and drains of the thin film transistors, and depositing and patterning pixel electrodes with a lower definition process.
The invention also relates to a method of manufacturing an active matrix LCD display including manufacturing an active plate using a method as described above; providing a passive plate; and sandwiching liquid crystal between the active and passive plates.
In another aspect, the invention relates to an active plate of a liquid crystal display manufactured using the method described above. The active plate may comprise an active plate for an active matrix liquid crystal device, comprising: a substrate; row conductors extending across the substrate; semiconductor regions extending over part of the row conductors forming the channel regions of thin film transistors; a metallisation layer defining the source and drain of the thin film transistors and column conductors connected to one of the source and drain; and pixel electrodes connected to the other of the source and drain of the thin film transistors.
The invention also relates to an active matrix liquid crystal display including such an active plate, a passive plate and in which liquid crystal is sandwiched between active and passive plates.